Abstract

Efficient summation of multiple operands in parallel is a critical aspect of various digital signal processing units. To accelerate this process, high compression ratio counters and compressors are indispensable. This study introduces a novel approach employing fast saturated binary counters and exact/approximate (4:2) compressors based on sorting networks. The inputs of the counter are asymmetrically divided into two groups and processed through sorting networks to generate reordered sequences, represented by one-hot code sequences. Through the establishment of three specific Boolean equations between the reordered and one-hot code sequences, the output Boolean expressions of the counter are significantly simplified. Simulation results demonstrate the superior performance of the proposed method compared to conventional approaches.

Description