ISSN 2394-5125
 

Research Article 


DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR

Sweety, Prachi Chaudhary.

Abstract
To improve the performance of the processors, the pipeline technique is used extensively to implement I.L.P (Instruction Level Parallelism). We measure the processor performance through the quantity of Instructions Level Parallelism represented through its design. We can counterstrike the parallelism with the aid of the execution of conditional branch instructions, which might additionally break the flow of the program execution. To overcome the branch problem, numerous ways have been suggested proactive to predict both the direction as well as the address of the executed instructions. In this paper, the FPGA ( Field Programmable Gate Arrays) based implementation of the 1-bit dynamic branch predictor is presented. The 1-bit dynamic branch predictor is developed especially for conditional branch instructions. The pipeline would not detach from the instruction queue when any conditional instructions occur as a 1-bit dynamic branch predictor implements it. This technique improves processor performance by implementing a deduction in the controlling hazard in the pipeline. Modelsim and Quartus tool is used for the design and implementation of the predictor.

Key words: Pipeline, branch prediction,1-bit dynamic branch predictor.


 
ARTICLE TOOLS
Abstract
PDF Fulltext
How to cite this articleHow to cite this article
Citation Tools
Related Records
 Articles by Sweety
Articles by Prachi Chaudhary
on Google
on Google Scholar


How to Cite this Article
Pubmed Style

Sweety , Prachi Chaudhary. DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR. JCR. 2020; 7(9): 1156-1162. doi:10.31838/jcr.07.09.212


Web Style

Sweety , Prachi Chaudhary. DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR. http://www.jcreview.com/?mno=115817 [Access: May 30, 2021]. doi:10.31838/jcr.07.09.212


AMA (American Medical Association) Style

Sweety , Prachi Chaudhary. DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR. JCR. 2020; 7(9): 1156-1162. doi:10.31838/jcr.07.09.212



Vancouver/ICMJE Style

Sweety , Prachi Chaudhary. DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR. JCR. (2020), [cited May 30, 2021]; 7(9): 1156-1162. doi:10.31838/jcr.07.09.212



Harvard Style

Sweety , Prachi Chaudhary (2020) DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR. JCR, 7 (9), 1156-1162. doi:10.31838/jcr.07.09.212



Turabian Style

Sweety , Prachi Chaudhary. 2020. DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR. Journal of Critical Reviews, 7 (9), 1156-1162. doi:10.31838/jcr.07.09.212



Chicago Style

Sweety , Prachi Chaudhary. "DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR." Journal of Critical Reviews 7 (2020), 1156-1162. doi:10.31838/jcr.07.09.212



MLA (The Modern Language Association) Style

Sweety , Prachi Chaudhary. "DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR." Journal of Critical Reviews 7.9 (2020), 1156-1162. Print. doi:10.31838/jcr.07.09.212



APA (American Psychological Association) Style

Sweety , Prachi Chaudhary (2020) DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR. Journal of Critical Reviews, 7 (9), 1156-1162. doi:10.31838/jcr.07.09.212