Abstract

Using the urdhva tiryaghbhyam algorithm and compressor from Vedic mathematics, this work focuses on the efficient design of low power arithmetic circuits such fast adders and multipliers. As the use of computers and signal processing grows, so does the need for fast processing. In many real-time signal and image processing applications, higher throughput arithmetic operations are crucial to achieve the needed performance. It has been of interest for decades to create fast adder and multiplier circuits, since these arithmetic operations are among the most important in such applications. One efficient and low-power multiplier is based on Vedic mathematics. Using this method in calculation algorithms will lessen the load on the system in terms of complexity, execution time, power consumption, etc. From which high-end digital circuits like the MAC unit and the FIR filter are constructed and analysed for efficiency in terms of both space and processing speed. Every digital signal processor has a media access control (MAC) unit, which is a basic building element in computers and is employed in many real-time signal processing modules. Multiplier, adder, and accumulator make up the MAC's core components. In digital signal processing, the MAC unit is responsible for performing complicated and continuous operations through repeated multiplication and accumulation. One of the primary considerations for facilitating quicker responses in real-time signal-processing applications is the design of an efficient MAC unit. Keywords: low power arithmetic circuits, Multiply and Accumulate, Digital Signal Processor (DSP), real time signal processing

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