Abstract

Day-by-day, the users of electronic devices such as computers, laptops, mobile phones, and tablets have been increasing gradually. Almost all people are using electronic devices or electronic gadgets every single day. So to satisfy the people’s need, we the engineers or the designers or the developers have to deal with the parameters, such as power consumption, area, energy required, and speed of the devices. There are so many design styles of adders available, such as Ripple carry adder, carry select adder, carry skip adder, Carry look-ahead adder, Carry increment adder, Carry save adder, and Carry bypass adder. The Ripple carry adder is the compact design among all available adders but the computation speed is too low. The Carry look ahead adders and Carry select adders are so fast as compared to Ripple carry adder. To design a high-speed low-power consumed with less area ICs, the designers have to focus on delay time, power consumption, and area occupied by the ICs. Different logic styles have been deliberately used to reduce the power consumption and increase the speed of the performance. Some of them are static CMOS logic, dynamic CMOS logic, dual rail domino logic, pseudo NMOS logic, pass transistor logic (PTL). Among these logic styles GDI technique is the most powerful technique used to reduce the power consumption, propagation delay and area of digital circuits, but the main disadvantage of PTL technique is that it will degrade the output. So, to overcome the problem faced with PTL technique, gate diffusion input (GDI) has been purposively used to design all the logic gates which are required to design a Carry look-ahead adder to achieve the parameters, like low power consumption, reduced delay time, energy efficient, and less transistor counts.

Description