Abstract

Digital signal processors (DSP) the endless requirement is the development of ability in processors to hold the difficulties resulted in the assimilation of CPU cores in a particular IC. Certain functions like convolution, transform, correlation and filtering are performed using digital signal processor. All these functions require multiplication and repetitive addition. So, multiply and accumulate unit (MAC) has significance in digital signal processor. High performance processes are of high importance in the MAC unit. Finally, DSP algorithms depend considerably on speed performance of MAC.Traditionally MAC architecture is implemented using the bit-parallel computing technique, which increases the hardware requirements quadratically as the bit precision increases. On the other hand, bit-serial computing reduces the hardware requirements by serializing one of the inputs and making the hardware size proportional to the bit precision. Moreover, with technology scaling there is a serious issue about static power dissipation. In this work, a high-speed MAC unit based on Sequential Finite-Field Multiplier (SFFM) technique is presented for Arithmetic Applications. The adder blocks in the MAC unit are designed using a high-speed Pipelined Adder architecture

Description