ISSN 2394-5125
 

Research Article 


A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION

S.Neelima, R.Brindha.

Abstract
Encryption is a mechanism where readable data is translated to unreadable format. It canít be accessed by intruder.
In biomedical application the medical data information should be secret. The paper presents the FPGA
implementation of a proposed hybrid method combining the features of SHA3 (Secure Hash Algorithm3 and AES
(Advanced Encryption Standard) algorithm for encrypting data during transmission. The proposed method is
compared with the Existing method which uses SHA and AES as encryption standard. The AES and SHA 3
algorithm is combined to increase the security level. It was observed from the results that the proposed method
improved the power consumption by around about 47 percent. The proposed encryption is new one of its own kind
in structure, operations and results. Using Quartus for Cyclone II, implementation is done in 90nm CMOS
technology.

Key words: Secure Hash Algorithm, CMOS, Security, Advanced Encryption Standard, Low power consumption, FPGA.


 
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Pubmed Style

S.Neelima, R.Brindha. A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION. JCR. 2020; 7(17): 1401-1413. doi:10.31838/jcr.07.17.180


Web Style

S.Neelima, R.Brindha. A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION. http://www.jcreview.com/?mno=29443 [Access: April 17, 2021]. doi:10.31838/jcr.07.17.180


AMA (American Medical Association) Style

S.Neelima, R.Brindha. A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION. JCR. 2020; 7(17): 1401-1413. doi:10.31838/jcr.07.17.180



Vancouver/ICMJE Style

S.Neelima, R.Brindha. A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION. JCR. (2020), [cited April 17, 2021]; 7(17): 1401-1413. doi:10.31838/jcr.07.17.180



Harvard Style

S.Neelima, R.Brindha (2020) A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION. JCR, 7 (17), 1401-1413. doi:10.31838/jcr.07.17.180



Turabian Style

S.Neelima, R.Brindha. 2020. A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION. Journal of Critical Reviews, 7 (17), 1401-1413. doi:10.31838/jcr.07.17.180



Chicago Style

S.Neelima, R.Brindha. "A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION." Journal of Critical Reviews 7 (2020), 1401-1413. doi:10.31838/jcr.07.17.180



MLA (The Modern Language Association) Style

S.Neelima, R.Brindha. "A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION." Journal of Critical Reviews 7.17 (2020), 1401-1413. Print. doi:10.31838/jcr.07.17.180



APA (American Psychological Association) Style

S.Neelima, R.Brindha (2020) A LOW POWER FPGA IMPLEMENTATION OF A HYBRID SHA3-AES DESIGN FOR ENCRYPTING DATA DURING TRANSMISSION. Journal of Critical Reviews, 7 (17), 1401-1413. doi:10.31838/jcr.07.17.180