Abstract

Very-Large-Scale Integration (VLSI) design makes use of Network-On-Chip (NOC) because it provides an appropriate connectivity topology and a practical alternative to system-on-chip. The lack of a clock in an asynchronous Network-On-Chip (ANOC) layout results in reduced power consumption. However, the computational complexity of attaining optimum path routeing in an ANOC is high. The total cost and the performance of an interconnection network are two important design concerns. The network's performance is determined by the topology configuration chosen and used by the routeing algorithm. The topology, switching process, and routeing algorithm are the primary determinants in ANOC design. In this study, we use an asynchronous mesh topology based on Hopfield Neural Networks (HNNs). The shortest path issue has been combined with a number of algorithms in an effort to improve routeing efficiency

Description