Abstract

Turbo codes are highly effective error correction codes widely employed in communication systems due to their superior error correction capabilities. This paper introduces a Very Large-Scale Integration (VLSI) architecture for the implementation of a Turbo decoder, enhancing the error correction process. Soft-in-soft-out decoders, interleavers, and deinterleavers, all utilizing the Maximum-a-Posteriori (MAP) algorithm, are integrated into the decoder. This MAP algorithm significantly reduces the number of iterations required for decoding transmitted information bits, optimizing the error correction process. On the encoder side, a system is utilized, incorporating two Recursive convolutional encoders and a pseudorandom interleaver. This approach enhances the encoding process, contributing to the overall reliability and efficiency of Turbo codes in communication systems.

Description