Abstract

The Modified Vedic Multiplier is a multiplication algorithm inspired by ancient Vedic Mathematics principles, employing a unique approach involving vertical and crosswise calculations. This research introduces the Modified HSCG-SCG Adder, an improved version of traditional binary adders, which employs a decoder to generate partial products and a carry tree to compute the final result. The synergy between the Modified Vedic Multiplier and the Modified HSCG-SCG Adder offers notable advantages over conventional multiplication methods, including reduced latency, lower power consumption, and increased processing speed. This combination is particularly well-suited for applications requiring high-speed multiplication, such as digital signal processing, image processing, and cryptography. The implementation of this algorithm is achieved through Verilog Hardware Description Language (HDL), enabling simulation and testing using hardware simulators like Vivado

Description