ISSN 2394-5125
 

Research Article 


ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj.

Abstract
In the current scenario of VLSI design Propagation delay, power dissipation, noise tolerance are
the major issues in low power high speed nan devices. The conventional CMOS technology suffers from sub
threshold leakage problems due to threshold voltage scaling of devices that cannot be adapted in sub-micron and
nano technologies. Looking for other alternatives Carbon Nano Tube FET (CNTFET) and Graphene
Nanoribbon FET (GNRFET) have emerged as possible candidates. The disadvantages are minimized when
GNRFET technology is scaled down in comparison to conventional MOS. as compared to silicon-based
transistors. This paper gives the comparative analysis of a 2 input NAND gate implemented using Domino logic
low power technique on CNTFET and GNRFET on the basis of average power dissipation. There is also
comparison of propagation delay (tp) and power delay product (PDP). The Simulations for the results obtained
have been performed with 14nm technology. The results clearly show that GNRFET structures have minimal
power dissipation and PDP in comparison to CNTFET based structures.

Key words: CNTFET, GNRFET, DOMINO LOGIC, POWER DELAY PRODUCT


 
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How to Cite this Article
Pubmed Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj. ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES. JCR. 2020; 7(19): 801-806. doi:10.31838/jcr.07.19.97


Web Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj. ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES. http://www.jcreview.com/?mno=102898 [Access: September 14, 2020]. doi:10.31838/jcr.07.19.97


AMA (American Medical Association) Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj. ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES. JCR. 2020; 7(19): 801-806. doi:10.31838/jcr.07.19.97



Vancouver/ICMJE Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj. ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES. JCR. (2020), [cited September 14, 2020]; 7(19): 801-806. doi:10.31838/jcr.07.19.97



Harvard Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj (2020) ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES. JCR, 7 (19), 801-806. doi:10.31838/jcr.07.19.97



Turabian Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj. 2020. ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES. Journal of Critical Reviews, 7 (19), 801-806. doi:10.31838/jcr.07.19.97



Chicago Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj. "ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES." Journal of Critical Reviews 7 (2020), 801-806. doi:10.31838/jcr.07.19.97



MLA (The Modern Language Association) Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj. "ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES." Journal of Critical Reviews 7.19 (2020), 801-806. Print. doi:10.31838/jcr.07.19.97



APA (American Psychological Association) Style

Sarthak Sharma, Shubham Mahajan,Arvind Rehalia, Amit Kant Pandit, Sumeet Gupta, Anil Kumar Bhardwaj (2020) ANALYSIS OF LOW POWER DESIGN TECHNIQUES FOR GNRFET AND CNTFET BASED DEVICES. Journal of Critical Reviews, 7 (19), 801-806. doi:10.31838/jcr.07.19.97